1. Field of the Invention
The invention relates to superconducting integrated circuit technologies and more particularly to a novel circuit element for use with such technologies.
2. Description of Related Art
Background information on superconducting technology may be found in Faris, "VLSI Superconducting Technologies," chapter 9 of Hardware and Software Concepts in VLSI, at 177-238 (1983) (hereinafter "Faris 1983") and in Zappe, "Josephson Computer Technology". Faris 1983 describes the well known Josephson junction in addition to many known superconducting circuit structures. It also points out many of the difficulties and limitations of known superconducting devices and circuits, including the following:
1. Inherent switching speed limitations. Most superconducting circuits which use Josephson junctions can be modelled as one of the three equivalent circuits shown in FIGS. 1(a), 1(b) and 1(c). FIG. 1(d) shows an equivalent circuit for the junction itself. When the junction in each such circuit switches from the novoltage state to the voltage state, a portion of the gate current I.sub.g is transferred to the load with the following transfer times for FIGS. 1(a), 1(b) and 1(c), respectively: ##EQU1## where C.sub.j is the junction capacitance, V.sub.g is the gap voltage of the junction, V.sub.out is the voltage across the junction, and R.sub.L and L.sub.L are the load resistance and inductance, respectively. The goal, of course, is to transfer as much of the current to the load as possible, as quickly as possible. These time periods are typically much larger and much more limiting than the intrinsic Josephson junction response time, which in the limit of zero junction capacitance is given by ##EQU2## where .DELTA. is the superconducting energy gap. The limitations are felt most severely in memory applications, where speed and density are extremely important. Typical memory configurations are described in Faris 1983 at 208-229; in Faris, et al., "Basic Design of a Josephson Technology Cache Memory," IBM J. Of Res. & Development , Vol. 24 (1980), pp. 143-154 (hereinafter "Faris, et al. 1980"); and in Gueret, et al., "Investigations for a Josephson Computer Main Memory with Single-Flux-Quantum Cells," IBM J. of Res. & Development, Vol. 24 (1980), pp. 155-166. It can be seen from these references that a typical memory operates through the transfer of current into and out of high impedance current paths (modelled like FIG. 1(a)) and/or long memory access loops (modelled like FIG. 1(b)). In order to improve speed, the Faris, et al. 1980 paper at p. 149 recognizes the desirability of using two series-connected driver gates (interferometers) instead of one. In circuits having transmission lines terminated with their characteristic impedance (FIG. 1(b a)), an improvement appears because two series-connected capacitors C.sub.j have an overall capacitance of C.sub.j /2. In circuits having an inductive characteristic (FIG. 1(b)), the improvement appears because the effective gap voltage doubles to 2V.sub.g. Both situations result in a halving of the relevant current transfer times. The halving of the overall capacitance also reduces the switching time by a factor of SQR(1/2) in FIG. 1(c) circuits.
This scheme for speeding up current transfer cannot be extended to more than 3 or 4 series gates, however, for several reasons. First, the speed benefits obtain only if all gates switch simultaneously, that is, only if the time required to transmit energy to the load is much greater than the time between switching of the first and last gate. Simultaneity is difficult to achieve since the gates are separated physically, and a certain amount of time is required for a control current to transverse the distance between one gate and another. The several gates must also be driven by a very fast buffer in order to minimize the effects of fabrication mismatch and in order to minimize the length of time that the junctions are in a grey region where they may or may not switch. Such buffers can occupy significant space on the chip and therefore reduce the overall density of the memory. Additionally, the several gates must be virtually identical in their construction in order that they respond identically to the control signal. This requires extremely tight fabrication tolerances which are difficult to achieve. Moreover, the driver gates must usually fit in the pitch between memory access loop conductors, because the drivers are usually placed along two adjacent edges (one for X and one for Y) of the memory cell array. If one driver circuit exceeds the pitch it will begin to overlap the space of the next driver circuit. Adding series driver gates therefore imposes undesirable limitations on the density of the memory cell array itself.
2. Resonance phenomena. It has been shown that the voltage-current relationship of a Josephson junction is governed by the following two equations: ##EQU3## where .phi..sub.1 and .phi..sub.2 are the phases of the superconductive order parameters of the two superconductors, V.sub.j is the voltage across the junction, and .PHI..sub.o is the unit flux quantum (2.07.times.10.sup.-15 Wb). If equation (2) is integrated and solved for .phi..sub.1 -.phi..sub.2, and the result inserted into equation (1), it can be seen that the current I.sub.j through the junction will oscillate according to the voltage across it. For a D.C. voltage V.sub.j =V.sub.dc, the Josephson oscillation frequency is approximately f.sub.j /V.sub.dc =483 GHz/mV. This is the so-called AC Josephson effect.
Many practical superconducting circuits use interferometers as the switching element instead of bare Josephson junctions. An example of a two-junction interferometers is shown in FIG. 2(a). As can be seen, the two junctions are connected together through an inductor, and the Josephson oscillations of each can be expected to influence the other. To a first approximation, the voltage across each junction becomes EQU V.sub.j =V.sub.dc +v.sub.o sin(.omega..sub.rf t)
When this is inserted into equations (1) and (2) above and the other components of the interferometer are factored in, it can be shown that the oscillations in current through the interferometer will appear at discrete resonance voltages of (2n+1)V.sub.r, where ##EQU4## L being the value of the main inductance and C.sub.j being the capacitance of each of the two junctions (considered for the purposes of this illustration to be equal). Interferometer resonances are described in Zappe and Landman, "Analysis of Resonance Phenomena in Josephson Interferometer Devices," J. Appl. Phys., Vol. 49, pp. 344-350 (1978).
The amplitude of the current steps in an interferometer can be sufficiently large that they interfere with the use of the device as the switching element in a circuit. This interference can be understood by referring to FIG. 2(b), which shows the interferometer I-V characteristic 10 with a resistive load line 12 shown superimposed thereon. A circuit such as that of FIG. 1(a) (with the junction replaced by an interferometer) will produce this type of characteristic. The interferometer curve 10 includes a portion 14 showing a nonzero Josephson gate current I.sub.g flowing when V=0, and two current steps 16 located at the fundamental and first harmonic voltages V.sub.r and 2V.sub.r.
It is assumed that the switching element is to be operated by varying the applied magnetic field such that the maximum Josephson current level of the interferometer reduces from I.sub.m to I.sub.m '. It is also assumed that the applied gate current I.sub.g is between I.sub.m and I.sub.m ' in magnitude. When the maximum Josephson current level is I.sub.m, the entire gate current I.sub.g flows through the junctions and the junctions remain in the no-voltage state. When the maximum Josephson current level is shifted down to I.sub.m ', the junction would ideally switch to the voltage state shown as 18 in FIG. 2(b). The voltage V.sub.v across the device would then be given by I.sub.g R, where R is the parallel combination of the load resistance R.sub.L (not shown in FIG. 2(a)) and the voltage dependent junction resistance R.sub.j (V).
However, as seen in FIG. 2(b), the amplitudes of some of the resonance current steps are large enough to intersect the load line 12. Consequently, instead of switching from V=0 to V=V.sub.v, the device may instead jump into one of the resonant modes represented by current steps 16. The device has a very low resistance in these modes, thereby preventing the desired current transfer to the load. Additionally, the device may jump from one resonant mode to another in an erratic manner. In any case it will be appreciated that the failure of the junction to switch immediately to V.sub.v hinders the junction's usefulness as a logic device. One solution to the resonance problem is described in U.S. Pat. No. 4,117,503 to Zappe. It involves connecting a damping resistor R.sub.d across the main inductance of the interferometer in order to dampen the resonances. This solution has limitations because the need to use a damping resistor of low inductance necessitates the use of a topology such as that shown in FIG. 5 of that patent. This may be undesirable or inconvenient in certain circumstances, and therefore imposes undue restrictions on circuit design flexibility. The topology also limits the achievable circuit density. Additionally, as reported by Harris in "Turn-on Delay of Josephson Interferometer Logic Devices," IEEE Trans. on Magnetics, Vol. MAG-15, pp. 562-565 (1979), the addition of a damping resistance introduces a turn-on delay factor not previously present.
Resonance phenomena also appear in bare Josephson junctions, if the junctions are made too large to be treated as "point" junctions. These are described in Zappe, "Dynamic Behavior of Josephson Tunnel Junctions in the Subnanosecond Range," J. Appl. Phys., Vol. 44, pp. 865-874 (1973), and one solution applicable in that context is given in U.S. Pat. No. 3,906,538 to Matisoo and Zappe.
3. Latching Property. A Josephson junction is normally a latching device. When it switches from the no-voltage state to the voltage state it will remain there indefinitely until the gate current is reduced to zero. This is inconvenient for logic applications because it means that an AC gate current must be used in order to periodically reset the device. The speed at which a combinational circuit can perform its function and be ready for more data is limited by the frequency of this AC gate current. Latching logic circuitry also requires a specialized power supply and power distribution scheme such as that described in Arnett and Herrell, "Regulated AC Power for Josephson Interferometer Latching Logic Circuits," IEEE Trans. on Maqnetics. Vol MAG-15, pp. 554-557 (1979).
To avoid these problems many circuits are designed to operate in a non-latching mode. Such a mode is achieved if the voltage V.sub.j across the device never exceeds the self-resetting voltage V.sub.min (.sub.c), given by ##EQU5## FIG. 3(a) shows the typical variation of V.sub.min as a function of an applied control current I.sub.c. It is periodic in I.sub.c, having a maximum and minimum value of V.sub.minh at V.sub.minl, respectively. These values are on the order of 0.4 mV. The shaded area below the curve represents the no-voltage state of the junction, and the area above the curve represents the voltage state. If the load is chosen such that V.sub.j in the voltage state is always below the curve, no amount of control current will cause the junction to switch into the voltage state. Alternatively, if V.sub.j is always above the curve, the junction will be in the voltage state even if I.sub.c is zero. Only if V.sub.j remains between V.sub.minl and V.sub.minh will the junction switch to the voltage state when an appropriate I.sub.c is applied, and then switch back to the no-voltage state (i.e., reset itself) when I.sub.c is removed. This is shown in FIG. 3(b).
Thus, in order to achieve non-latching operation, the load must be chosen such that V.sub.v, the voltage across the junction when it is in the voltage state, is between V.sub.minl and V.sub.minh. This is a very small range, requiring tight processing tolerances which are difficult to meet. Also, as shown in FIG. 3(b), the usable range of control currents I.sub.c is also limited. Additionally, in circuits where the load is a terminated transmission line, the transmission line impedence must be very small, on the order of 1 ohm, in order to obtain the desired load line slope. Such transmission lines must be made very wide, which results in low density, low speed and low yield.
4. Gain. A Josephson junction is a two terminal device having a gain defined as I.sub.g /I.sub.c. When biased near its threshold, this gain can be large in principle. In practice it is often less than unity, however, because the junction is biased well below its threshold to avoid inadvertent switching by noise sources and to accommodate parameter variations that are inevitable in the LSI environment. By arranging a plurality of junctions in inductive networks (interferometer circuits) or resistive networks (current injection circuits), a gain larger than unity is obtainable. For example, in transformer-coupled devices such as interferometers, a current gain can be achieved by using a large inductance in the control winding or by using more than one control winding. But such gain is always at the expense of more area, and it necessitates tight control on parameter tolerances to achieve high chip yield. The crucial parameters are threshold current I.sub.m (I.sub.c), power regulation, resistors, and junction capacitance. The threshold current variations are the most challenging ones to control at tolerances below 10% since they depend on variations in area and current density. The latter depend on the tunnel barrier thickness. Since the barrier thickness is only tens of angstroms, it has to be uniform within fractions of an angstrom as a result of the exponential thickness dependency of the tunneling probability. Moreover, resort to interferometer structures to achieve current gain is undesirable because it introduces resonances, as described above. No superconducting device proposed to date has been able to achieve a voltage gain for large signals.
The difficulty in obtaining gain renders multi-stage circuits difficult to design and fabricate. It also renders communication from the cryogenic environment to the room temperature environment difficult, since the voltage swings used in superconducting circuits are in the millivolts and the voltage swings used in room temperature technologies are in the volts. A large voltage gain would be required for effective communication.
5. Isolation. In order for a switching element to be most useful, it is desirable that the output signal be isolated from the input signal. That is, an appropriate change in the input signal should affect the output signal, but any change in the output, even if due to external influences, should have an affect on the input which is at most negligible. A bare Josephson junction, being a two-terminal device, does not satisfy this condition. Transformers, which are four-terminal passive elements, are used to provide isolation in Josephson circuits. The primary carries the input I.sub.c, and the secondary is either the junction itself (in which case the magnetic field of the transformer acts directly to lower the critical current level), or a separate loop connected to the junction (in which case a current is induced, adding to I.sub.g and switching the junction as its critical current is exceeded). The latter is shown in FIG. 2(a). Transformer coupling is only an artificial means for achieving isolation, however, and does not operate at the microscopic level of the Josephson device itself. It therefore is much larger than the physical scale of the films and barriers used in the junction. Circuit density is limited not by the active element, but by the passive element needed to provide isolation.
A three-terminal superconducting transistor is disclosed in U.S. Pat. No. 4,157,555 to Gray. This device provides isolation, but is severely limited in many other respects. In particular, it must be fabricated using materials which are sub-optimal from a superconducting viewpoint, and its output level is too small for use in digital applications. In U.S. Pat. No. 4,334,158, there is described another superconducting device, called a Quiteron, which solves or avoids many of the problems described above. The Quiteron is described further in Faris, "Quiteron," Physica, Vol. 126B, pp. 165-175 (1984). It comprises a tunnel junction which has a threshold power density above which the superconducting gap of the superconducting electrode vanishes. The device operates via a heavy injection of quasi-particles into the superconductor, and does not use the Josephson effect. However, Quiterons do not have sufficient voltage gain and do not exhibit a large enough voltage swing. Quiterons are also relatively slow devices, even slower than the Josephson junction.